Metal Oxide Semiconductor (MOS) devices are widely used today in ultra large scale integrated (ULSI) devices. MOS devices include memory devices which are comprised of an array of memory cells. Each memory cell is comprised of a capacitor, on which the charge stored represents the logical state of the memory cell. Long conductors, referred to as word lines, serve as gates of multiple access transistors, each of which provides access to a memory cell.
In a dynamic random access memory (DRAM) a common word line is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide (SiO.sub.2), known as gate oxide. Word lines currently are formed on the gate oxide layer as a two-layer stack, comprising silicon (or polysilicon), coated with a conductor material such as tungsten silicide or titanium silicide.
Of primary concern is minimizing resistivity throughout the word line due to the need to reduce RC time constants and access multiple memory cells in as short a period of time as possible. The problem is especially critical due to the extended length of word lines as DRAMs increase in density.
As DRAM density increases, feature sizes, including line sizes, decrease. For example, when the feature size of a conductor, such as tungsten or titanium silicides, is reduced in higher density memories, the Kelvin contact resistance of the conductor increases. Titanium silicide is a large grain material. Thin titanium silicide has nonuniform large grain size that contributes to a very rough titanium silicide/silicon interface. As such, it reduces the effective ohmic contact area. It is therefore desirable to utilize conductors that have smaller grains and hence whose resistivity will not significantly increase for the same feature dimensions.
Conductors utilizing near noble metal silicides, such as CoSi.sub.2 have low bulk resistivity and a fine grain with very small line-width dependent Rs effects. They are well suited for sub-quarter micron conductor formation such as polycide word lines or bit lines. However, they are very difficult to pattern because of the nonvolatile nature of cobalt fluorides and chlorides during a dry etch process. Conventional methods of patterning CoSi.sub.2 polycide gate electrodes for DRAM devices require extra masks to pattern insulating layers or spacers. A Co salicidation is then used on fill-in Si (poly). The extra masks can significantly increase costs of DRAM devices.
There is a need to decrease the overall resistivity of a word line stack and local interconnects at sub-quarter micron dimensions. There is a need to precisely pattern CoSi.sub.2 conductors and word line stacks without introducing additional masks. There is a further need to precisely etch such conductors and word line stacks in an inexpensive manner.